Welcome to the Predictive
Technology Model (PTM) website! PTM provides accurate,
customizable, and predictive model files for future transistor and
interconnect technologies. These predictive model files are compatible with
standard circuit simulators, such as SPICE, and scalable with a wide range of
process variations. With PTM, competitive circuit design and research can start
even before the advanced semiconductor technology is fully developed.
As an evolution of previous
Berkeley Predictive Technology Model (BPTM), PTM will provide
the following novel features for robust design exploration toward the 10nm
- Predictions of various transistor structures, such
as bulk, FinFET (double-gate) and ultra-thin-body SOI, for sub-45nm
- New methodology of prediction, which is more
physical, scalable, and continuous over technology generations.
- Predictive models for emerging variability and
reliability issues, such as NBTI.
To benchmark your design for
nanoscale MOSFETs, download the latest PTM model cards or
generate your own CMOS and interconnect models
PTM-MG for multi-gate devices, such
as bulk FinFET, from 20nm to 7nm nodes. Two versions are offered,
high-performance (HP) and low-standby power (LSTP). This is jointly developed
with ARM. The model files
and some brief explanation are available from
- 11/15/2008: PTM LP for low-power design is released,
from 45nm to 16nm nodes. In conjunction with PTM HP, it provides more choices for
various design applications.
- 9/30/2008: PTM HP for high-performance design
applications is released, covering 45nm to 16nm nodes. PTM HP incorporates latest technology
advances, including high-k/metal gate and strained silicon. A alternative
choice for low-power design applications, PTM LP, is going to released soon.
PTM releases the predictive model for metallic carbon nanotube (CNT-interconnect),
based on a similar modeling approach as that of
CNT-FET. Verilog-A codes and the manual are available from
PTM releases a new version for sub-45nm bulk CMOS, providing new modeling
features on metal
gate/high-k, gate leakage, temperature effect, and body bias.
PTM releases the first predictive model for
carbon nanotube FET (CNT-FET).
- 2/11/2007: The tool of Nano-CMOS
is implemented to nanoHUB, accessible at https://www.nanohub.org/simulation_tools/nanocmos_tool_information.
- 12/15/2006: The beta
version of PTM for 22nm bulk CMOS is released.
- 8/31/2006: The beta version of Nano-CMOS,
an online tool to customize your own PTM files, is released. You can
define your own inputs and obtain both nominal and variational model
cards through Nano-CMOS.
- 4/28/2006: The beta version of PTM for NBTI is
released for 250nm to 32nm nodes.
- 2/22/2006: A new generation of PTM for bulk CMOS
technology is released for 130nm to 32nm nodes. The new PTM captures the
latest technology advances. It achieves better scalability and
continuity across technology generations.
- 9/30/2005: PTM for 32nm bulk, 32nm FinFET, and
45nm FinFET technologies are available.
developed by the Nanoscale
Integration and Modeling (NIMO) Group at ASU. This project is sponsored
by FCRP Focus
Center for Circuit and System Solutions (C2S2) and Materials Structures and
Devices Center (MSD), and by Semiconductor
Research Corporation (SRC).
International Technology Roadmap for Semiconductors (ITRS)
BSIM developed by by the Device Group, University of California,
at Purdue University