INTERCONNECT


Estimate the line-to-ground and line-to-metal capacitances/inductances for your interconnect design!


For each technology generation, two structures are analytically modeled. Typical interconnect technology parameters are listed as the last part of this page. Their values are generated from literature survey including International Technology Roadmap for Semiconductors.

Please select your benchmarking structure from below:


Structure 1


Coupling lines above one metal ground (for top global layer)


Structure 2


Coupling lines between two metal ground planes (for local and intermediate layers)



For both structures, by setting line space (s) >> line width (w), you can calculate the RLC values for a single line.



Appendix: Typical wire dimensions

  • 65nm technology node
  width (um) space (um) thickness (um) heightILD (um) kILD
Local 0.10 0.10 0.20 0.20 2.2
Intermediate 0.14 0.14 0.35 0.20 2.2
Global 0.45 0.45 1.20 0.20 2.2
  • 90nm technology node
  width (um) space (um) thickness (um) heightILD (um) kILD
Local 0.15 0.15 0.30 0.30 2.8
Intermediate 0.20 0.20 0.45 0.30 2.8
Global 0.50 0.50 1.20 0.30 2.8
  • 0.13um technology node
  width (um) space (um) thickness (um) heightILD (um) kILD
Local 0.20 0.20 0.45 0.45 3.2
Intermediate 0.28 0.28 0.45 0.45 3.2
Global 0.60 0.60 1.20 0.45 3.2
  • 0.18um technology node
  width (um) space (um) thickness (um) heightILD (um) kILD
Local 0.28 0.28 0.45 0.65 3.5
Intermediate 0.35 0.35 0.65 0.65 3.5
Global 0.80 0.80 1.25 0.65 3.5




Last updated 09/30/2005. Questions? Contact us.

Copyright 2005, Nanoscale Integration and Modeling (NIMO) Group, ASU. All rights reserved.